From 98a672123c7872f6b9b75a9a2b6bb3aea504de6a Mon Sep 17 00:00:00 2001
From: David Leutgeb <david.leutgeb@mannundmouse.com>
Date: Tue, 5 Dec 2023 12:25:34 +0100
Subject: Initial commit

---
 MIBS/cisco/CISCOSB-SCT-MIB | 47 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 MIBS/cisco/CISCOSB-SCT-MIB

(limited to 'MIBS/cisco/CISCOSB-SCT-MIB')

diff --git a/MIBS/cisco/CISCOSB-SCT-MIB b/MIBS/cisco/CISCOSB-SCT-MIB
new file mode 100644
index 0000000..a83b1f6
--- /dev/null
+++ b/MIBS/cisco/CISCOSB-SCT-MIB
@@ -0,0 +1,47 @@
+CISCOSB-SCT-MIB DEFINITIONS ::= BEGIN
+
+-- Title:      CISCOSB Switch Interfaces Private
+-- Version:    7.50
+-- Date:       16 Aug 2010
+
+IMPORTS
+    OBJECT-TYPE, Counter32                         FROM SNMPv2-SMI
+    TruthValue                                      FROM SNMPv2-TC
+    switch001                                       FROM CISCOSB-MIB;
+
+rlSctMib MODULE-IDENTITY
+        LAST-UPDATED "201008161234Z"
+        ORGANIZATION "Cisco Systems, Inc."
+
+        CONTACT-INFO
+        "Postal: 170 West Tasman Drive
+        San Jose , CA 95134-1706
+        USA
+
+        
+        Website:  Cisco Small Business Support Community <http://www.cisco.com/go/smallbizsupport>"
+
+        DESCRIPTION
+            "The private MIB module definition for SCT MIB."
+        ::= { switch001 203 }
+
+--rlSctCpuRateEnabled
+rlSctCpuRateEnabled OBJECT-TYPE
+    SYNTAX      TruthValue
+    MAX-ACCESS  read-write
+    STATUS      current
+    DESCRIPTION
+        "Indication whether the counter CPU rate is enabled"
+    ::= { rlSctMib 1 }
+
+--rlSctCpuRate
+rlSctCpuRate OBJECT-TYPE
+    SYNTAX      Counter32
+    MAX-ACCESS  read-only
+    STATUS      current
+    DESCRIPTION
+        "the amount of packets per second the CPU is handling."
+    ::= { rlSctMib 2 }
+
+END
+
-- 
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